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| QL24x32B pASIC(R) 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS Very High Speed - ViaLink(R) metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. High Usable Density - An 24-by-32 array of 768 logic cells provides 8,000 usable ASIC gates (14,000 PLD gates) in 144-pin TQFP, 208-pin PQFP and 208-pin CQFP packages. PCI-Output Drive - Fully PCI 2.1 compliant input/output capability. (including drive current) Low-Cost, Easy-to-Use Design Tools - Designs entered and simulated using QuickLogic's new QuickWorks(R) development environment, or with third-party CAE tools including Viewlogic, Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place and route on PC and workstation platforms using QuickLogic software. ...8,000 usable ASIC gates, 180 I/O pins 4 pASIC 1 QL24x32B Block Diagram 768 Logic Cells = Up to 172 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells 4-31 QL24x32B PRODUCT SUMMARY The QL24x32B is a member of the pASIC 1 Family of very-high-speed CMOS user-programmable ASIC devices. The 768 logic cell fieldprogrammable gate array (FPGA) offers 8,000 usable ASIC gates (equivalent to 14,000 PLD gates) of high-performance general-purpose logic in 144-pin TQFP and 208-pin PQFP and CQFP packages. Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today's fastest microprocessors and DSPs. Designs can be entered using QuickLogic's QuickWorks Toolkit or most populart third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software. Ample on-chip routing channels allow fast, fully automatic place and route of designs using up to 100% of the logic and I/O cells, while maintaining fixed pin-outs FEATURES Total of 180 I/O pins - 172 Bidirectional Input/Output pins - 6 Dedicated Input/High-Drive pins - 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks - PCI 2.1 Compliant I/Os Input + logic cell + output delays under 6 ns Chip-to-chip operating frequencies up to 110 MHz Internal state machine frequencies up to 150 MHz Clock skew < 0.5 ns Input hysteresis provides high noise immunity Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming 144-pin TQFP compatible with QL16x24B 0.65 CMOS process with ViaLink programming technology 4-32 QL24x32B Pinout Diagram 144-pin TQFP 4 pASIC 1 4-33 QL24x32B Pinout Diagram 208-pin PQFP/CQFP PIN # 1 PIN # 157 pASIC QL24X32B-1PQ208C PIN # 105 PIN # 53 4-34 QL24x32B PQFP/CQFP 208 Function/Connector Table PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 FUN I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/Sck I/Clk PIN 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 FUN VCC I/P I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O PIN 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 FUN I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND PIN 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 FUN I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O PIN 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 FUN I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/SI I/Clk PIN 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 FUN VCC I I/SO VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O PIN 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 FUN I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND PIN 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 FUN I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O 4 pASIC 1 4-35 QL24x32B ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................. -0.5 to 7.0V Input Voltage ....................... -0.5 to VCC +0.5V ESD Pad Protection .................................. 2000V DC Input Current...................................... 20 mA Latch-up Immunity................................. 200 mA Storage Temperature .......-65C to + 150C Lead Temperature ...................................300C OPERATING RANGE Symbol VCC TA TC K Parameter Supply Voltage Ambient Temperature Case Temperature -X Speed Grade Delay Factor -0 Speed Grade -1 Speed Grade -2 Speed Grade Military Min Max 4.5 5.5 -55 125 0.39 0.39 1.82 1.56 Industrial Min Max 4.5 5.5 -40 85 0.4 0.4 0.4 0.4 2.75 1.67 1.43 1.35 Commercial Min Max 4.75 5.25 0 70 0.46 0.46 0.46 0.46 2.55 1.55 1.33 1.25 Unit V C C DC CHARACTERISTICS over operating range Symbol VIH VIL VOH VOL II IOZ CI IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage [0] Output LOW Voltage [0] Input Leakage Current 3-State Output Leakage Current Input Capacitance [1] Output Short Circuit Current [2] D.C. Supply Current [3] Conditions Min 2.0 3.7 2.4 VCC-0.1 0.4 0.1 10 10 10 -90 160 10 Max 0.8 IOH = -4 mA IOH = 16 mA IOH = -10 A IOL = 24 mA* IOL = 10 A VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND Unit V V V V V V V A A pF mA mA mA -10 -10 -10 40 *IOL = 24 mA for commercial range only. IOL = 12 mA for the industrial and military ranges. Notes: [1] [2] [3] [4] Capacitance is sample tested only. CI = 20 pF max on I/(SI). Only one output at a time. Duration should not exceed 30 seconds. Commercial temperature grade only. Maximum Icc for industrial grade is 15mA and for military grade is 20 mA. For AC conditions use the formula described in the Section 9 -- Power vs Operating Frequency. Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. These limits are derived from a representative selection of the slowest paths through the pASIC logic cell including net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. [5] 4-36 QL24x32B AC CHARACTERISTICS at VCC = 5V, TA = 25C (K = 1.00) Logic Cell Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Propagation Delays (ns) Fanout 2 3 4 2.1 2.7 3.3 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.7 2.0 2.0 2.0 2.0 2.0 2.0 2.2 2.7 3.3 1.9 2.3 2.8 1.9 1.9 1.9 1.8 1.8 1.8 8 5.5 2.1 0.0 4.9 2.0 2.0 5.5 4.6 1.9 1.8 Input Cells Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 3.1 3.3 1.4 2.7 2.0 2.0 Propagation Delays (ns) [4] 2 3.2 3.4 1.9 2.8 2.0 2.0 3 3.3 3.5 2.3 2.9 2.0 2.0 4 3.4 3.6 3.0 3.0 2.0 2.0 8 4.4 4.6 4.8 3.1 2.0 2.0 12 5.8 6.0 6.7 3.3 2.0 2.0 16 6.5 6.7 8.5 3.4 2.0 2.0 4 pASIC 1 Output Cell Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Notes: [6] [7] [8] See High Drive Buffer Table for more information. Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. tPHZ 1K The following loads are used for tPXZ: 5 pF 1K tPLZ 5 pF Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 2.1 2.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.3 3.8 4.3 3.6 4.5 5.3 2.6 3.1 3.7 3.3 4.1 4.9 150 5.4 6.9 4.8 6.5 4-37 QL24x32B High Drive Buffer Symbol Parameter Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 5.8 7.2 5.0 7.1 5.8 6.7 7.7 5.9 6.8 6.0 7.4 5.2 7.3 6.0 6.9 7.9 6.1 7.0 tIN High Drive Input Delay tINI High Drive Input, Inverting Delay AC Performance Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. The AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The effects of voltage and temperature variation are illustrated in the graphs on page 4-47, K Factor versus Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts specific timing parameters for precise path analysis or simulation results following place and route. ORDERING INFORMATION QL 24x32B - 1 PQ208 C QuickLogic pASIC device Operating Range C = Commercial I = Industrial M = Military M/883C = MIL STD 883 Package Code PF144 = 144-pin TQFP PQ208 = 208-pin PQFP CF208 = 208-pin CQFP pASIC device part number B = 0.65 micron CMOS Speed Grade X = quick 0 = fast 1 = faster 2 = fastest 4-38 |
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